J. Cent. South Univ. (2017) 24: 2582-2595

DOI: https://doi.org/10.1007/s11771-017-3672-9

Open-circuit fault diagnosis and fault tolerance for shunt active power filter

PENG Tao(彭涛), ZHAO Shuai(赵帅), DAN Han-bing(但汉兵), YU Hua-xiong(玉华雄)

School of Information Science and Engineering, Central South University, Changsha 410083, China

Central South University Press and Springer-Verlag GmbH Germany, part of Springer Nature 2017

Abstract: The open-circuit fault of the power switches in shunt active power filter (SAPF) would exacerbate the harmonic pollution of power grid, and degrade the reliability of the devices and system. A fault diagnosis method is proposed based on reference model and an over-modulation strategy under hardware fault tolerance for SAPF. First, a mathematic model is established for SAPF. Second, the residuals are generated by comparing the outputs of reference model and those of actual model, and open-switch fault is detected and diagnosed by residual evaluation. After that, hardware fault tolerance is performed with the three-phase four-switch (TPFS) topology to isolate the faulty phase. Finally, the over-modulation strategy is proposed to increase the voltage transfer ratio of the TPFS topology. Simulation and experimental results verified the feasibility and effectiveness of the proposed method.

Key words: fault diagnosis; fault tolerant; reference model; over-modulation; three-phase four-switch topology; shunt active power filter

1 Introduction

With the massive use of electronic devices, nonlinear loads and distributed resources, harmonic pollution of power grid has become increasingly prominent. The harmonic pollution considerably reduces the efficiency of power grid, and disturbs the stable operation of other power equipment. Shunt active power filter (SAPF), with the function of harmonic suppression and reactive power compensation, has attracted a lot of attention [1, 2].

Power switches, the core part of SAPF, which operate under the condition of high switching frequency and thermal stress for a long time, are prone to failure or damage [3]. If an open-switch fault occurred, the operation performance of SAPF would deteriorate, and it would exacerbate the harmonic pollution of power grid. Meanwhile, other normal switches have to bear overcurrent and overheating. These conditions combined with uninterrupted operation for a long time may cause a series of problems, such as component ageing and parameter drift, which would eventually lead to the failure rate increase and reliability degradation of the devices and system [4]. Therefore, it is crucial to find a real-time monitoring and a fault diagnosis method to improve the reliability of SAPF.

Fault diagnosis methods are divided into analytical model and data driven method [5]. Reference model method is to generate the output difference between reference model and actual model. Then, the output difference is used as a residual and is compared with a predefined threshold. If the residual is greater than the threshold, there is a failure. This method has been applied to the open-switch fault diagnosis in cycloconverter diver system, advanced static var generation (ASVG) and voltage-source inverter (VSI) [6–8]. However, issues on diagnosing the open-switch fault of SAPF based on reference model have been paid little attention to [9].

Fault tolerant is an effective technique to improve the reliability of power electronic system [10]. Fault tolerant methods are classified into hardware-based method and software-based method [11, 12]. Three kinds of hardware-based fault tolerant topologies, parallel redundant, phase redundant and three-phase four-switch (TPFS), have already been applied to SAPF system [13]. The TPFS topology does not need any extra power switch and cooling equipment [14, 15], but the voltage transfer ratio reduces by half, compared with the normal operation’s [16]. In Refs. [17, 18], the reference voltage of DC-link is set as two times the normal operation’s to achieve the expected value. Under this condition, the voltage of normal switches would be increased a lot, so as the power loss. Therefore, it is necessary to increase the voltage transfer ratio without greatly raising the DC-link reference voltage with the TPFS topology.

The over-modulation strategy was proposed in 1993 by HOLTZ et al [19] for the first time, and it was applied to the modulation algorithm of inverter to raise the voltage transfer ratio. Currently, over-modulation strategy has been widely applied to the VSI [20–22]. However, with the TPFS topology, researches on over-modulation strategy for increasing the voltage transfer ratio have rarely been seen.

This paper proposes an open-switch fault diagnosis and fault tolerant scheme for SAPF. At first, a reference model fault diagnosis method is proposed to locate the faulty switch. A TPFS topology is used for hardware fault tolerance, and an over-modulation strategy is proposed to increase the voltage transfer ratio of the TPFS topology. Simulation and experimental results are presented respectively to verify the validity and feasibility of the proposed method.

2 Open-circuit fault diagnosis based on reference model

2.1 Open-circuit fault analysis

The six-switch SAPF topology is shown in Fig. 1.e_a, e_b and e_c denote the grid voltages; i_a, i_b and i_c represent the compensating currents of SAPF; v_an, v_bn and v_cn denote the output voltages of the SAPF; v_ao, v_bo and v_co denote the phase voltages of the SAPF; i_sa, i_sb and i_sc represent the grid currents; i_La, i_Lb and i_Lc represent the load current; v_La, v_Lb and v_Lc denote the load voltages; D_k and D′_k are the antiparallel diodes, k=a, b or c; C_dc represents the DC-link capacitor; v_dc is the voltage of C_dc; L_s denotes the impendence of the electric wire, and the value of L_s is small enough to be neglected; L_f is the filter inductance;

Suppose that all devices are ideal. The structure of S_k (k=a, b or c) under normal and open-circuit fault condition are shown in Figs. 2(a) and (b).

Fig. 1 Circuit diagram of six-switch SAPF topology

Introduce switching function c_k to indicate the on or off state of switch S_k and S′_k.

                      (1)

Output voltage v_kn under normal and S_k open-circuit fault condition is shown in Table 1.

Fig. 2 Structure of S_k (k=a, b, c) under normal(a) and open-circuit(b) fault condition

Table 1 Output voltage v_kn under normal and S_k open-circuit fault condition

2.2 Reference model establishing

The relationship between the phase voltage and the compensating current is shown as follows:

                         (2)

Transform Eq. (2) into two dimensions under dq axis as

            (3)

where ω denotes the fundamental frequency of grid; i_d and i_q represent the compensating current under dq axis; v_do and v_qo represent the output voltage under dq axis; e_d and e_q represent the grid voltage under dq axis.

Take the model under normal condition as the reference model, which is described as

            (4)

whereare the compensating currents of reference model, which are regarded as the references of i_d and i_q; are the phase voltages of reference model, which are regarded as the references of v_do and v_qo.

Discretize Eqs. (3), (4) as

                 (5)

                 (6)

where T is the sampling period; i_d(k), i_q(k), and are the kth sampling data of i_d, i_q, and i_d(k–1), i_q(k–1), …, are the (k–1)th sampling data of relevant variables.

2.3 Residual generating

Compare the outputs of actual model with those of the reference model, and define the residual under dq axis r_d(k), r_q(k) as

                (7)

Substitute Eqs. (5), (6) into Eq. (7):

  (8)

where v_do(k), v_qo(k), are calculated by following equations:

                 (9)

                (10)

Three-phase residual r_a(k), r_b(k) and r_c(k) are obtained after Clarke transformation as

(11)

2.4 Fault detection

For the existence of dead-zone time, forward conductive voltage, saturation voltage and other characteristics of power device, the residual obtained in Section 2.3 may be not zero even if no open-circuit fault occurs. So, an appropriate threshold is necessary to avoid misdiagnosis of SAPF system.

According to the principle of the maximum instantaneous value, the threshold of fault detection v_th is defined as

                (12)

where are the dead-zone voltage of SAPF; m is a dynamic parameter, which is set after a series of experiments. The misdiagnosis rate will increase if the value of m is too small, while the missing rate will increase if m is too big.

Define the flag of residual ε_k (k=a, b, c) as follows:

                           (13)

When ε_k=0, it indicates that no fault exists in the SAPF; while ε_k=1 or ε_k=–1 indicates that the SAPF might be operating under open-circuit fault condition. The relationship between the value of ε_k and fault location is presented in Table 2.

Table 2 Relationship between value of ε_k and fault location

To avoid noise and other disturbance, fault duration time T_f is introduced. The value of T_f is an integral multiple of system period, which is determined by some experiments.

Define fault sensitivity coefficient k_f as

                                 (14)

Define flag of fault detection F_k(a,b,c) as follows:

                   (15)

If any one of F_a, F_b and F_c equals 1, an open-circuit fault is considered to occur in the SAPF.

2.5 Fault diagnosis

The value of F_k is relevant to the open-circuit fault location of SAPF. The flag of fault diagnosis is defined as F_T. Combined with flag of fault detection F_k, a decision table is established, as shown in Table 3. After the detection of the open-circuit fault, the faulty switch is located by checking this table.

Table 3 Decision table of fault diagnosis

In conclusion, the implementation process of open- circuit fault diagnosis is shown in Fig. 3.

3 Hardware fault tolerance with over- modulation strategy

3.1 TPFS hardware fault tolerant topology

The hardware fault tolerant topology of SAPF is presented in Fig. 4, where C₁ and C₂ are the DC-link capacitors; v_dc1 and v_dc2 are the voltage of C₁ and C₂; TR_a, TR_b, TR_c are the bidirectional thyristors. TR_a, TR_b and TR_c are off when SAPF operates under normal condition [16].

If a power switch is open-circuit, the faulty switch could be located by the fault diagnosis method proposed in Section 2. The switching driving signal is set to zero to isolate the faulty leg. Meanwhile, these two power switches of faulty phase are replaced by two split capacitors. The bidirectional thyristor is triggered on and the node k (k=a, b, c) of faulty phase is connected with the neutral point of the DC-link capacitor.

If the open-circuit fault occurs in S_a, set the switching driving signal of S_a, S′_a to zero to isolate leg a. Next, trigger TR_a to connect node a to the neutral point n. The SAPF topology changes into TPFS topology, as shown in Fig. 5.

After hardware fault tolerance, the voltage transfer ratio decreases by half. As a consequence, the amplitude of maximum output voltage of the SAPF drops by half if the DC-link reference voltage is not changed.

3.2 Over-modulation strategy under TPFS topology

If the open-circuit fault occurs in S_a, there are four on-off states (c_b, c_c) of leg b and c, (0, 0), (0, 1), (1, 0) and (1, 1). The relationship between output voltage of SAPF and the on-off states of switch is expressed as

                 (16)

The relationship between DC-link reference voltage vector U_r and output voltage of SAPF is expressed as

                (17)

Four basic voltage vectors, corresponding to four on-off states, are represented by U₀, U₁, U₂ and U₃. The relationship between the basic voltage vectors and the components of reference voltage vector U_r in two- dimension stationary frame is shown in Table 4. The vector space is divided into 4 quadrants by the four basic voltage vectors, as shown in Fig. 6, where θ_r denotes the angle between reference voltage vector U_r and α axis.

Reference voltage vector U_r is composed by two adjacent basic voltage vectors at any part of the vector space. Taking quadrant 1 for example, U_r is composed by U₀ and U₁, and the action time of those two basic voltage vectors is expressed as

                       (18)

where T_r1 and T_r2 are the action time of U₀ and U₁ respectively; zero vector is added to complement a switching period, which is equaled by introducing two opposite voltage basic vectors at the same time, and the action time of zero vector is denoted by T_r0; T_s is the switching period.

Fig. 3 Sketch of implementation process for open-circuit fault diagnosis

Fig. 4 Hardware fault tolerant topology of SAPF

Fig. 5 TPFS topology when S_a is open

Table 4 Relationship between u_α, u_β and basic voltage vectors

Space vector pulse width modulation (SVPWM) is used for SAPF under TPFS topology and the implementation process is shown in Fig. 7, where T_b and T_c are the duty ratio of SVPWM under TPFS topology.

Define modulation index M as follows:

                            (19)

Connect the endpoint of the four basic voltage vectors and a rhombus is formed. When the track of reference voltage vector is tangent with the margin of rhombus, When the track is beyond the margin of the rhombus, M>0.5774, which is called the over-modulation. There are three over- modulation zones as

                      (20)

Under the condition of over-modulation, the relationship between actual output voltage vector and output voltage of SAPF is expressed as

              (21)

where U_nk (k=I, II, III) is the actual output voltage vector compensated by compensating voltage vector in over-modulation zone k.

Fig. 6 Voltage vectors of SAPF under TPFS topology

Taking vector space quadrant 1 for example, three over-modulation zones are analyzed.

1) Over-modulation zone I

The voltage vectors of over-modulation zone I are shown in Fig. 8, where the reference voltage vector U_r1 is represented by dotted circular arc. A compensate voltage vector U_c1 is added, represented by the thin solid line FG, and the compensating areas are ABFE and CDHG. The heavy line EFGH represents the actual voltage vector U_n1. φ₁ is the angle between basic voltage vector U₀ and OF, where F is the intersection of compensating voltage vector U_c1 and the margin of rhombus. By geometric analysis, the range of φ₁ is fixed, that is 0<φ₁≤π/6.

Fig. 7 Implementation process of SVPWM under TPFS topology

Fig. 8 Voltage vectors of over-modulation zone I

According to Fig. 8, the amplitude of compensating vector U_c1 is expressed as

                   (22)

The amplitude of actual voltage vector U_n1 is expressed as

        (23)

After Fourier transformation, the fundamental component of |U_n1| is expressed as

                     (24)

To compensate the part of U_r1 beyond the margin of rhombus, set:

                                 (25)

On the basis of Eqs. (19), (23), (24) and (25), the relationship between M and φ₁ is shown as

(26)

From Eq. (26), the graph of relationship between M and φ₁ is plotted in Fig. 9.

Fig. 9 Relationship between M and φ₁ in zone I

On the basis of given reference voltage vector, the modulation index M is calculated. If it is in the over-modulation zone I, the magnitude of φ₁ is obtained by checking Fig. 9. Then, the amplitude of compensating voltage vector U_c1 is figured out by Eq. (22). Regard U_c1 as the reference voltage vector, and the action time of the basic voltage vectors is calculated by Eq. (18). After the compensation, the track of the reference voltage vector is beyond the margin of the rhombus, T_r1+T_r2>T_s. Equation (27) is modified as

                         (27)

2) Over-modulation zone II

The voltage vectors of over-modulation zone II are shown in Fig. 10.

Same as zone I, the reference voltage vector U_r2 is represented by the dotted circular arc. There are only one intersection of U_c2 and MN, and the compensating area is CDGF. The heavy line MFG represents the actual voltage vector U_n2. φ₂, represented by is the angle between basic voltage vector U₀ and OF. By geometric analysis, the range of φ₁ is fixed, that is 0<φ₂≤π/2.

According to Fig. 10, the amplitude of compensating vector U_c2 is expressed as

Fig. 10 Voltage vectors of over-modulation zone II

                 (28)

The amplitude of actual voltage vector U_n2 is expressed as

          (29)

On the basis of Eqs. (19), (24), (25) and (29), the relationship between M and φ₂ is shown as

                 (30)

From Eq. (30), the graph of relationship between M and φ₂ is plotted in Fig. 11.

Fig. 11 Relationship between M and φ₂ in zone II

On the basis of given reference voltage vector, the modulation index M is calculated. If it is in the over-modulation zone I, the implementation process is the same as over-modulation zone II.

3) Over-modulation zone III under hardware fault tolerance

The voltage vectors of over-modulation zone III are shown in Fig. 12, where φ₁, represented by is the holding angle of the actual voltage vector. In over-modulation zone III, the margin of rhombus is inside of compensating voltage vector. To ensure the maximum of output voltage, U_n3 should be held at a vertex for a while until the phase angle of reference voltage vector θ_r equals φ₁. When θ_r=π/2–φ_h, U_n3 is held at the other vertex of rhombus.

Fig. 12 Voltage vectors of over-modulation zone III

The amplitude of actual voltage vector U_n3 is expressed as

      (31)

On the basis of Eqs. (19), (24), (25) and (31), the relationship between M and φ₁ is shown as

                     (32)

From Eq. (32), the graph of relationship between M and φ₁ is plotted in Fig. 13.

Fig. 13 Relationship between M and φ₁ in zone III

If the modulation index M is in the over-modulation zone III, by checking Fig. 13, the magnitude of φ₁ is obtained.

I) (n=1, 2, 3, 4), where n is the quadrant number of the vector space.

When U_r is located in first quadrant or third quadrant, Eq. (27) is modified as

                                  (33)

When U_r is located in second quadrant or fourth quadrant, Eq. (27) is modified as

                                  (34)

II) (n=1, 2, 3, 4).

Equation (27) is modified as

                      (35)

Based on the analysis above, the implementation process of over-modulation strategy under the TPFS topology is shown in Fig. 14.

4 Simulation results

To illustrate the effectiveness of the proposed method of fault-diagnosis and fault tolerance, a simulation model of SAPF system has been developed based on Matlab/Simulink software. The parameters of the simulation model are listed in Table 5.

In this work, m and k_f are chosen as 0.8, 10, respectively.

4.1 Fault diagnosis

Set the occurring time of S_a open-switch fault as 0.1 s. Figure 15 shows the waveforms of the compensating current i_a, i_b, and i_c before and after an open-circuit fault.

As we can see in Fig. 15, after the occurrence of open-circuit fault in S_a, the waveform of i_a is distorted, and most parts over zero are chopped.

Figure 16 shows the waveforms of grid current i_sa, i_sb and i_sc before and after an open-circuit fault occurs in S_a. Figure 17 shows the spectrum of i_sa before and after the open-circuit fault.

As we can see in Figs. 16 and 17, the grid current is distorted due to the S_a open-circuit fault, and harmonic distortion rate increases to 11.96% from 2.20%.

Figure 18 shows the waveforms of the residual r_a, r_b and r_c during the simulation. Figure 19 shows the flags of residual ε_a, ε_b and ε_c.

The residual r_a, r_b and r_c are not always zero before

Fig. 14 Implementation process of over-modulation strategy under TPFS topology

Table 5 Parameters of SAPF system simulation model

Fig. 15 Compensating current i_a (a), i_b (b) and i_c (c) with S_a open-circuit

the occurrence of the open-circuit fault, which illustrates the necessity of the threshold, as shown in Fig. 18. After the occurrence of open-switch fault, the value of residual r_a, r_b and r_c change a lot, ε_a=–1, ε_b=1, ε_c=1, as shown in Fig. 19, consistent with the theory analysis.

Fig. 16 Grid current i_sa, i_sb and i_sc before and after fault

Fig. 17 Spectra of i_sa before (a) and after (b) fault

Figure 20 shows the flag of fault detection F_k and the flag of fault diagnosis F_T during the simulation.

After the occurrence of open-circuit fault in S_a, the value of F_a changes into 1 and the values of F_b and F_c remain 0. While F_T changes into 1 from 0, as shown in Fig. 20. It is diagnosed that an open-circuit fault had occurred in S_a by checking Table 3.

It takes 1.28 ms to accomplish the open-circuit fault diagnosis, which is faster than switching function model based method in Ref. [23] (9.6 ms) and park vector based method in Ref. [6] (20 ms).

Fig. 18 Waveforms of residual r_a (a), r_b (b) and r_c (c)

4.2 Fault tolerance

After fault diagnosis, the fault tolerance is applied in SAPF system. Two tolerant simulations are carried out in this work, a) hardware fault tolerance and b) hardware fault tolerance with over-modulation strategy.

a) Hardware fault tolerance. The topology of SAPF changes into the TPFS topology, as shown in Fig. 5. Set the amplitude of DC-link reference voltage to 1400 V.

Figures 21 and 22 show the waveforms of compensating current i_a, i_b, i_c and grid current i_sa, i_sb, i_sc before and after hardware fault tolerance. Figure 23 shows the spectrum of i_sa after hardware fault tolerance.

As we can see in Figs. 21 and 22, SAPF system begins compensating grid current normally after hardware fault tolerance. The distortion rate of i_sa is 4.19%, as shown in Fig. 23.

Fig. 19 Flags of residual ε_a (a), ε_b (b) and ε_c (c)

b) Hardware fault tolerance with over-modulation strategy. The topology of SAPF changes into the TPFS topology, as shown in Fig. 5. Set the amplitude of DC-link reference voltage to 1122 V and over- modulation strategy under TPFS topology proposed in Section 3.2 is applied.

Figures 24 and 25 show the waveforms of compensating current i_a, i_b, i_c and grid current i_sa, i_sb, i_sc before and after hardware fault tolerance with over-modulation strategy respectively. Figure 26 shows the spectrum of i_sa after hardware fault tolerance with over-modulation strategy.

In Figs. 24 and 25, SAPF system begins compensating grid current normally after applying over-modulation strategy under TPFS topology. The distortion rate of i_sa is 4.39%, as shown in Fig. 26.

Fig. 20 Flag of fault detection F_k and flag of fault diagnosis F_T:

Fig. 21 i_a, i_b and i_c before and after hardware fault tolerance

Fig. 22 i_sa, i_sb and i_sc before and after hardware fault tolerance

Fig. 23 Spectrum of i_sa after hardware fault tolerance

Fig. 24 i_a, i_b and i_c before and after hardware fault tolerance with over-modulation strategy

Fig. 25 i_sa, i_sb and i_sc before and after hardware fault tolerance with over-modulation strategy

Fig. 26 Spectrum of i_sa after hardware fault tolerance with over-modulation strategy

The simulation results can be seen clearly in Table 6.

Table 6 Simulation results

5 Experimental results

To further verify the effectiveness of the fault diagnosis method and fault tolerance strategy, a hardware-in-loop (HIL) verification platform has been developed in laboratory. The HIL platform includes three parts, real-time simulator dSPACE, physical controllers and upper computer, as shown in Fig. 27. The parameters of the platform are listed in Table 5.

Fig. 27 Set up of the HIL verification platform in laboratory

First, build the discrete model of main circuit of SAPF, power switches and other key components in Fig. 4 using Xilinx software. Then compile and download the discrete model to dSPACE. The strategies of fault-diagnosis and fault tolerance are written to the physical controller which is connected with dSPACE by high-speed I/O data interface. The process of the experiment is monitored and regulated by the upper computer. The structure of the HIL verification platform is shown in Fig. 28.

Fig. 28 Sketch of HIL verification platform

Set the occur time of S_a open-switch fault as 0.1 s. Figure 29 shows the waveform of the compensating current i_a, i_b and i_c before and after the open-circuit fault.

As we can see in Fig. 29, after the occurrence of open-circuit fault in S_a, the waveform of i_a changes a lot.

Figure 30 shows the flag of fault diagnosis F_T during the experiment.

The SAPF topology changes into the TPFS topology after fault diagnosis, as shown in Fig. 5. Set the amplitude of DC-link reference voltage to 1122 V and Over-modulation strategy under hardware fault tolerance proposed in Section 3.2 is applied. The response waveform of DC-link reference voltage and actual voltage are shown in Fig. 31.

After v_dc reachesthe waveform of DC-link voltage is stable.

Figure 32 shows the waveforms of i_sa, i_sb and i_sc before and after hardware fault tolerance with over-As we can see in Fig. 32, the gird current is distorted when the open-circuit fault occurs in S_a. After hardware fault tolerance with over-modulation strategy, the gird current returns to normal, the distortion rate is 4.58%, the magnitude of DC-link reference voltage is lower than that of traditional method (1400 V), and the voltage transfer ratio is increased. The experimental results are consistent with the simulation results in Section 4.

Fig. 29 Compensating current i_a, i_b and i_c before and after fault

Fig. 30 Flag of fault diagnosis F_T during experiment modulation strategy.

Fig. 31 DC-link reference voltage and actual voltage v_dc

Fig. 32 Grid current i_sa, i_sb, i_sc before and after hardware fault tolerance with over-modulation strategy

6 Conclusions

In this work, the open-circuit fault of the power switches in SAPF is analyzed and a fault diagnosis method based on model reference and an over- modulation strategy under hardware fault tolerance are proposed. When an open-switch fault occurs, the performance and reliability of SAPF would be degraded. The proposed fault diagnosis method generates an indication to locate the faulty switch. Hardware fault tolerance with over-modulation strategy is applied to decrease the distortion rate of the grid current, reduces the magnitude of DC-link reference voltage and increase the voltage transfer ratio. The proposed fault diagnosis method and fault tolerant strategy are easy to implement in real time. Simulation and experimental results verified the feasibility and effectiveness of the proposed method.

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(Edited by YANG Hua)

Cite this article as: PENG Tao, ZHAO Shuai, DAN Han-bing, YU Hua-xiong. Open-circuit fault diagnosis and fault tolerance for shunt active power filter [J]. Journal of Central South University, 2017, 24(11): 2582–2595. DOI:https://doi.org/10.1007/s11771-017-3672-9.

Foundation item: Project(2012AA051601) supported by the High-Tech Research and Development Program of China

Received date: 2016-05-17; Accepted date: 2016-09-05

Corresponding author: DAN Han-bing, PhD Candidate; Tel: +86–15200815824; E-mail: HanbingDan@csu.edu.cn